The present invention relates, in general, to automated design of integrated circuits, and more particularly to floorplanning for an integrated circuit which utilizes a macrocell array structure.
During the physical design process of a large, structured integrated circuit a floorplanning step, i.e. the automatic placing of logic, memory and other elements on the integrated circuit, has proven to be highly useful. Not only is the probability of successfully completing the physical layout increased by such a preliminary step, but the computer time and manual effort taken to complete this step is also reduced. One such floorplanner is found in U.S. Pat. No. 4,918,614, issued Apr. 17, 1990, to H. Modarres et al., which is incorporated herein by reference. The floorplanner described by Modarres et al examines the connectivity net list in an attempt to first place groups of cells in the most advantageous position, then to assign connections to routing channels so as to best assure successful completion of routing. The floorplanner estimates the probability of success based on the routing wires balanced by the actual space that is estimated to be required for routing these connections. However, this estimate does not take into account enough of the many variables that affect the success of this highly complex physical design process.
There is a need for a floorplanner which provides a highly reliable estimate of the probability for success during the balance of the physical design process. The floorplanner should incorporate a graphical interface to allow manual editing of the floor plan, a fast global router to allow accurate determination of the wire length contribution for each connection, a graphical display which will accurately indicate the areas of congestion to the designer, and which will allow manual editing of the floorplanning process. Since the entire process of floorplanning, cell placement, and interconnect routing are highly complex the floorplanner must incorporate both theoretical and empirical rules which take into account the complex components affecting success of the physical design process. The floor planner should derive an initial suitability score for the design based on the netlist information that accurately predicts the difficulty expected when completing the physical design. The floorplanner must then allow the floorplan to be manually altered for optimization. A more accurate suitability score should be readily derived to guide this optimization. Finally the floorplanner should output files that can interact directly with other physical design tools allowing very accurate prediction of integrated circuit timing without spending the computer time and expense required to actually design and test the integrated circuit.